Phase Locked Loops are circuits well known in the communications arts, for synchronizing a variable local oscillator with the phase and/or frequency of a component of a transmitted signal. Typically such circuitry includes a phase detector which is responsive to the transmitted signal and the output of the local oscillator, to generate a phase error signal proportional to the difference in those between a component of the transmitted signal and the oscillator output. The phase error signal is coupled to control the oscillation rate of the variable oscillator. In order to enhance the operation the PLL, some systems include a second loop which generates an error signal proportional to the difference between the frequency of the variable oscillator and the frequency of the component of the transmitted signal. The frequency error signal is added to the phase error signal for controlling the rate of the oscillator. Nominally the variable oscillator will achieve the desired frequency before phase lock is achieved, at which time the frequency error signal is substantially zero, and the PLL is controlled by only the phase error signal. That is, near phase lock the frequency error signal is, for the most part, inherently disconnected.
It has been suggested, that in certain PLL systems it may be desirable to actively disconnect the frequency error signal when phase lock is approached. Actively disconnecting the frequency error term will preclude noise in the frequency error signal from causing jitter in the phase of the signal provided by the variable oscillator. Phase jitter is particularly problematic in PLL's including frequency error circuitry arranged to respond to digitized signals, for example PLL's responsive to the pulse code modulated (PCM) representation of the subcarrier burst of a composite video signal. U.S. Pat. No. 4,884,040, issued to R. T. Fling (which is incorporated in its entirety herein by reference) exemplifies such a PLL. The present inventors have found that the performance of a Fling type PLL may be significantly improved by actively disconnecting the frequency error term when the system approaches phase lock.
Detecting phase lock in analog PLL systems is typically accomplished by mixing the component of the transmitted signal with the output from the variable oscillator shifted by 90 degrees and low pass filtering the result. This process is not easily emulated with digital circuitry for operation on PCM samples however, because the realization of digital mixers (i.e. multipliers) requires hundreds of transistors.